1. Field of the Invention
The present invention relates generally to the testing of integrated circuit dies. More specifically, but without limitation thereto, the present invention relates to mapping logic failures on an integrated circuit die to find a location of a physical feature in the integrated circuit die that is common to multiple failed test paths.
2. Description of Related Art
The combination of logic tests for specific logic paths and computer automated design (CAD) navigation tools that can map the physical paths in an integrated circuit die allows the physical path of a failed test or net across the die to be displayed and plotted. The plots from a number of tests performed on different dies for identical test paths may be combined to produce a stacked map for displaying the locations of the highest number of failures to identify physical features on the die that are most likely to be the cause of the failed nets.